The present invention relates to a controller for a printing unit, and more particularly to such a controller having a central or system bus and a local bus for delivering data to the printing unit.
Known controllers for printing units have a standard hardware board provided with a central processing unit, an I/O-unit, and a central bus system connected to the central processing unit and the I/O-unit. The I/O-unit has a connector for connecting the central bus system to a memory board that comprises one or more memory chips for storing bitmap data or compressed bitmap data of a page to be printed, and a memory reader for reading the bitmap data and transmitting them to a printer.
A controller of this type is used in high-speed printing units such as laser printers or the like for supplying the image data to be printed to the print engine in the form of a pixel bit stream with a sufficient transmission rate, so that they may readily be printed. Accordingly, the controller must be capable of handling large amounts of image date in a relatively short time.
Although it is possible to provide a controller specifically designed for this purpose, manufacturing costs can be reduced by utilizing standard hardware components as they are used in normal data processing systems.
FIG. 2 illustrates an example of a prior art controller for a printing unit which has the advantage that the central processing unit (CPU) 10, the I/O-unit 12 and the central bus system 14 are formed by a standard hardware board as it is used for example in workstations. The I/O-unit 12 has a number of connectors 16, 18, 20 to which extension boards can be connected for driving peripheral devices such as memories, keyboards, or for providing interfaces to a host computer or the like. The extension boards connected to the connectors 16-20 can communicate with the central processing unit 10 and with one another via the central bus system 14.
One connector 16 is specifically designed for connecting a memory board 22 that comprises one or more memory chips 24. The memory chips 24 may for example be formed by single in-line memory modules (SIMMs) and serve as a bitmap memory. A bitmap reader 26 (memory reader) is connected to another connector 18 of the I/O-unit 12 and is capable of transmitting the read image data to the printer 28.
The data of a page to be printed are assembled in the bitmap memory under the control of the CPU 10. When a page is completed, the bitmap reader 26 gets control over the central bus system 14 and reads the bitmap data from the memory chips 24 and transmits them sequentially to the printer 28.
This conventional controller has the disadvantage that the central bus system 14 is occupied during the time when the bitmap reader 26 is operating, so that no other tasks can be performed during this time. This disadvantage is avoided in another prior art design which is illustrated in FIG. 3. Here, the bitmap reader 26 has been replaced by another processor 30, a so-called raster image processor (RIP) which can communicate with a bitmap memory 34 via a local bus 32. Thus, the bitmap memory 34 is not directly connected to the I/O-unit 12. The bitmap data are assembled and read by the raster image processor 30. As a consequence, the central bus system 14 is available for other tasks while the raster image processor 30 is operating. However, the disadvantage is that a second processor in addition to the CPU 10 is necessary.
U.S. Pat. No. 5,122,973 discloses a controller similar to that shown in FIG. 3, in which the raster image processor is used only for assembling the bitmap data and dedicated hardware is provided for reading the bitmap and transmitting the data to the printer.
It is an object of the present invention to provide a controller for a printing unit which can be based on a standard hardware board and permits more efficient use of the central bus system, without requiring a second processor.
This object is achieved by a controller for a printing unit that provides a memory board that has a second bus system directly connecting the memory chips to the memory reader.
In this context, xe2x80x9cdirectlyxe2x80x9d means that the central bus system is not needed for the transmission of data from the memory chips to the memory reader, i.e. the memory chips are on the one hand linked to the central bus system in order to receive compressed or non-compressed bitmap data therefrom, and are on the other hand connected to the memory reader via a second bus system which operates independently from the central bus system. Thus, when the bitmap data are read, the central bus system is not occupied and is available for any other tasks which are to be performed by the central processing unit.
It will be noted that this advantage is achieved without requiring a second processor or any other substantial modification of the prior art systems. All that is needed is a modification of the memory board to provide it with the second bus system. From the viewpoint of the central bus system, the memory board nevertheless behaves like a normal memory board which can be fitted to the main board as usual.
In a preferred embodiment, the memory chips are formed by single in-line memory modules (SIMMs) and the bitmap reader is provided directly on the memory board together with the SIMMs.
The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.